Conserving resources, including energy, has become a pre-eminent objective in today's world. Manufacturers of ICs are sensitive to the need to improve the energy efficiency of their products. Those skilled in the pertinent art are aware that various measures may be taken in an electronic circuit to reduce its power consumption. One measure is to use cells (i.e., logic elements including devices, e.g., transistors) that leak less current when turned off. Another measure is to use a lower voltage to drive the cells. Unfortunately, using lower leakage current cells or lower drive voltages almost always reduces the speed at which signals propagate through the circuit. Consequently, the circuit may not operate as fast as needed or desired.
Thus a fundamental trade-off exists among speed and power consumption. Further considerations involve speed, power consumption, area and yield. These force the circuit designer to employ EDA tools, particularly timing signoff, to strike a delicate balance. Tempering the designer's zeal are the above-described process and environmental variations to which every production circuit is subject. These variations increase the degree to which the designer must ensure that production circuits work under real-world operating conditions and therefore the complexity of timing signoff.
Further complicating the designer's task is the difficulty of determining the consequences of design choices, particularly when they involve different technology nodes. In other words, a designer may not have the information needed to make optimal decisions regarding the technology node or nodes to employ to fabricate a particular IC design.
Voltage scaling is a technique whereby the drive voltage to a particular IC is modulated to one or more particular values such that the IC can function properly (e.g., the circuit operates as fast as needed or desired). Voltage scaling is particularly suited to compensate for process variations. Static voltage scaling may be performed at the factory (e.g., during calibration) or before the IC begins normal operation (e.g., during power-up initialization). In contrast, adaptive voltage scaling and optimization (AVSO) is performed continually while the IC is in normal operation and particularly effective at compensating for temperature variations and device aging as well as process variations. ICs can have one or more domains, each having its own voltage regulator. Drive voltage can therefore be modulated separately in each domain, allowing compensation for on-chip-variations (OCV) to be carried out as well.
Voltage scaling (including AVSO), therefore, can be used to compensate for process and temperature variations and aging in an IC that has been designed by a conventional method. Additionally, voltage scaling can be used to change the fundamental theory under which an IC operates. Accordingly, the method by which an IC is designed may be transformed to take full advantage of the benefits of voltage scaling. Thus, voltage scaling can be used when designing ICs such that their performance, area, power consumption, yield or any combination of these may be improved beyond the limits of current design methods. As such, it would be beneficial in the art to be able to accurately determine the benefits provided by voltage scaling techniques including, for example, AVSO.